Verilator

CodeRabbit runs Verilator to find issues in Verilog and SystemVerilog files.

Verilator is a static analysis tool for Verilog and SystemVerilog hardware designs.

CodeRabbit runs Verilator v5.052.

Files

Verilator runs on changed files with the following extensions:

• .v
• .sv

Configuration

enabled · boolean · default: true

Enable Verilator: Verilator lints Verilog and SystemVerilog for syntax, width, connectivity, and behavioral correctness issues.

.coderabbit.yaml

.coderabbit.yaml

reviews:
  tools:
    verilator:
      enabled: true

Web UI

In your organization or repository settings, go to Reviews → Tools and turn the tool on or off with its toggle.

Findings appear inline with Verilator rule identifiers, affected line ranges, and severity.

Security policy and restrictions

CodeRabbit runs Verilator in a sandbox with a fixed lint-only invocation. It does not load repository-supplied plugins, command files, compiler flags, or generate executable models.

Profile behavior

Verilator uses the same invocation in Chill and Assertive modes.

When we skip Verilator

CodeRabbit skips Verilator when:

• The pull request has no changed .v or .sv files.
• reviews.tools.verilator.enabled is set to false.
• Verilator is already running in GitHub Actions, GitLab CI, CircleCI, or Azure Pipelines.

Links

• Verilator homepage
• Verilator user guide